Conventionally, a NAND type flash memory and a NOR type flash memory which can program and erase, are widely adopted in a non-volatile semiconductor memory device. Recently, there have been greater demands for an increase in speed of the program operation in not only a NAND type flash memory but also in a NOR type flash memory. In a conventional NOR type flash memory, an N channel type transistor is adopted. The N channel type transistor of the NOR type flash memory conducts a program operation by CHE (Channel Hot Electron) injection. However, the number of memory cells which could be simultaneously programmed in a program operation by CHE injection could not be increased. The number of memory cells at the time of program operation could not be increased due to a memory cell current which flowed at a few hundred μA and it was difficult to improve a program throughput. Also, there is need to apply a high level voltage of about 4V between the source and the drain in the memory cell transistor. And with the application of the high voltage, a problem is created where there is limit to the miniaturization of a gate length direction.
In order to solve these problems, the inventors of the present invention have already proposed a program technology which adopts an electron injection method as cited in, for example, Japan Laid Open Patent 2006-156925. This technology provides a P channel type cell transistor programmed by a band to band tunnel (below referred to as BTBT) phenomenon instead of CHE injection in a program operation.
FIG. 1 is a circuit diagram which shows one block in a conventional non-volatile semiconductor memory device. FIG. 2 is a cross section drawing of a bit line direction in a conventional non-volatile semiconductor memory device. The memory cells MC00a, . . . , MCn0a, MC00b, . . . , MCn0b, MC01a, . . . , MCna, MC01b, . . . , MCn1b which are P channel type transistors and the selection transistors ST0a, ST1a, ST0b, ST1b are formed within the same N well region in a conventional non-volatile semiconductor memory device. The N well region is separated into each block. Within one block, two sub bit lines SBL0a, SBL1a, . . . , SBL0b, SBL1b, . . . are connected to each main bit line MBL0, MBL1, . . . .
FIG. 3 shows a timing diagram during a conventional program operation. FIG. 3 is made to correspond to the operation during program of the memory cell MCn0a in FIG. 1
First, in FIG. 3, at the time t1 the operation during program of the memory cell MCn0a, the word lines WL<0>, . . . , WL<n>, the main bit lines MBL0, MLB1, . . . , the selection gates SGa, SGb, a source line SL and the N well region are all set at a voltage Vcc. Next, at the time t2, the voltage of the selected word line WL<0> is boosted from Vcc to VPwl. The voltage of the N well region of the memory cell MCn0a is boosted from Vcc to VPnwell. Also, the voltage of the selection gate SGa of the memory cell MCn0a is lowered from Vcc to VNsg. At this time, the selection transistors ST0a and ST1a in the selection gate SGa are ON. The voltage of the sub bit lines SBL0a and SBL1a becomes Vcc, the same voltage as of the main bit lines MBL0 and MBL1.
On the other hand, the selection transistors ST0b and ST1b in the unselected selection gate SGb are connected to the sub bit lines SBL0b and SBL1b. The voltage of the sub bit lines SBL0b and SBL1b is boosted by the capacitive coupling of the N well region and the memory drain junctions. However, the boost level of the capacitive coupling is cramped by the voltage Vcc+|Vthp| which may be the conducting level of the selection transistors ST0b and ST1b. Here, the voltage Vthp is the threshold voltage of the selection transistors ST0b and ST1b. At the time t3, when a “0” data program is done to the cell MCn0a, the voltage of the main word line MBL0 becomes 0V from Vcc. The sub bit line SBL0a is connected to the drain of the memory cell MCn0a which is to be programmed. The voltage of the sub bit line SBL0a becomes 0V.
At this time, the word line WL of the selected memory cell MCn0a for programming is at VPwl. The drain of the memory cell MCn0a is at 0V. The source line SL is at Vcc. The N well region of the memory cell MCn0a is at VPnwell. As a result, the electrons in the BTBT current which occurs around the area of the drain of the memory cell MCn0a are accelerated toward the channel direction. The electrons are attracted to the side of the word line which is applied with a positive voltage VPwl. As a result, electrons are injected into a floating gate of the memory cell MCn0a. This is the program operation of the memory cell MCn0a. After this, at the time t4, the program operation is finished by returning the voltage of the main bit line MBL0 of the memory cell MCn0a to Vcc. At the time t5, each voltage of the memory cell MCn0a is returned to its initial state.
This technology is described in Japanese laid open patents 2006-156925, 2006-128594 and 2006-259697 and Ajika et al., “A Flash Memory Programmed at 100 MByte/second is Developed”, Nikkei Electronics No. 938, pp 137-148 (2006).
By the proposal stated above of the inventors, it is possible, in a non-volatile semiconductor memory device, the voltage applied between a source and a drain of a memory cell transistor is reduced when compared with the voltage applied between a source and a drain of a conventional memory cell transistor. However, the problem of disturbance is likely to occur in the unselected memory cell transistor during program operation. The problem of disturbance occurs particularly on the memory cell transistor which is connected to an unselected bit line and a selected word line. In other words, it is strongly desired to provide a method, wherein a high voltage is not applied between the source and drain, a required voltage for a program operation is applied between the source and drain of the memory cell to be programmed, and a program inhibit voltage of a level where disturbance does not become a problem is selectively and efficiently applied.
For example, a disturbance problem in a program operation in a conventional example shown in FIG. 1 will be described. Memory cell transistors other than the memory cell transistor MCn0a to be programmed suffer from the disturbance. Specifically, the memory cell transistors MCn0b, MCn1a, MCn1b . . . which are not the cell to be programmed are located along the word line which is the selected word line WL<n>. There is a great danger that a disturbance problem will occur in the memory cell transistors MCn0b, MCn1a, MCn1b . . . which are not to be programmed. A disturbance problem occurs when the drain voltage of the unselected memory cell transistor MCn1a which connected to the same selection gate SGa and is connected to the sub bit line SBL1a is at Vcc. The drain voltage of the memory cell transistor MCn0a which is to be programmed is at 0V. This is because the voltage difference between the drain voltage of the memory cell transistor MCn1a which is not to be programmed and the drain voltage of the memory cell transistor MCn0a is only Vcc. Here, if the drain voltage Vcc of the memory cell transistor MCn1a, which is not to be programmed, is a low voltage, then a problem occurs where selectivity becomes worse. For example, when Vcc is 1.8V, there is a need to control the program selection or non selection (inhibit) by this 1.8V voltage difference.
Also, similarly, the voltage which is applied to the source of the memory cell transistor MCn1a which is not to be programmed is also Vcc. The same disturbance problem as the drain occurs in the source side. Because of this, there is need to secure sufficient selectivity against program disturbance which occurs in the source side.
On the other hand, because the drain voltage of the memory cell transistors MCn0b, MCn1b which are connected to SBL0b, SBL1b which are selected by the selection gate SGb which is different to the selection gate SGa which the selected memory cell transistor MCn0a is connected, is boosted up to Vcc+|Vthp| by capacitive coupling between the N type well region and the junction of the drain of the memory cell transistor, therefore, the drain voltage of the memory cell transistors MCn0b and MCn1b becomes a higher level than Vcc. However, across the entire non-volatile semiconductor memory device, the memory cell transistor which is connected to the sub bit line which is selected by the same selection gate as the memory cell transistor which is selected, receives the strongest disturbance. Therefore, disturbance characteristics are not sufficient.
As stated above, in order to improve disturbance characteristic during programming, there is a need to increase selectivity by making the drain voltage of the non-programming memory cell higher than Vcc. However, when a method of charging by a high voltage from the side of the main bit line MBL is adopted, a loss in consumption energy and high voltage setup time occurs. This is because there is a need to charge a voltage which is not to be programmed to all the main bit lines MBL. Also, according to this method, in the case where a main/sub bit line construction is adopted in which a plurality of sub bit lines SBL are connected to one main bit line MBL as shown in FIG. 1, a problem occurs whereby the above stated voltage cannot be applied to the cell connected to the same main bit line MBL. Therefore, by a method other than the method stated above, it is strongly desired that the voltage between the source and the drain of the memory cell transistor which is to be programmed continue to be controlled and be made higher than only the drain voltage Vcc of the non-programming memory cell. The improvement of the program disturbance which occurs on the source side is also demanded.
It is the prime object of the present invention to provide a non-volatile semiconductor memory device to overcome the above mentioned problems. However, other object of the present invention will be well described in the forgoing descriptions.